Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores

Single-issue processor cores are very energy efficient but suffer from the von Neumann bottleneck, in that they must explicitly fetch and issue loads/storse necessary to feed their ALU/FPU. Each instruction spent on moving data is a cycle not computation, limiting ALU/FPU utilization 33 percent reductions. We propose “Stream Semantic Registers” boost increase efficiency. SSR lightweight, non-invasive RISC-V ISA extension which implicitly encodes memory accesses as register reads/writes, eliminating large number of loads/stores. implement proposed RTL an existing multi-core cluster synthesize design for modern 22 nm technology. Our provides significant, 2x 5x, architectural speedup across different kernels at small 11 core area. Sequential code runs 3x faster single core, fewer needed achieve same performance. The almost 100 leads efficiency improvement cluster. reduces fetches by up 3.5x cache power consumption 5.6x. Compilers can automatically map loop nests SSRs, making changes transparent programmer.